The invention relates to a digital circuit having a filter unit for suppressing glitches.
A known digital circuit is formed of logic circuit units to which an input signal is intended to be fed via an input of the digital circuit. Corresponding output signals are then established at outputs of the circuit units. Since, under certain circumstances, the input signal may have glitches, which are not intended to have an effect on the signals at the outputs, a filter is provided to which the input signal perturbed by glitches is fed and which generates from this a signal which is free from glitches. The filtered signal is then fed to the circuit units.
The prior art described has the disadvantage that the use of the filter unit, which produces the filtered signal to be delayed relative to the input signal, increases the overall delay or signal propagation delay between the input signal and the output signals at the outputs. The delay between the output and the input is calculated for example from the sum of the delay caused by the filter unit and the delay caused by the first circuit unit.
U.S. Pat. No. 4,716,318 describes a low-pass filter for an integrated circuit which has two low-pass filter elements disposed essentially in parallel with one another, of which elements one is provided for the purpose of filtering positive glitches and one is provided for the purpose of filtering negative glitches, and which elements are logically combined with one another on the output side via a flip-flop formed by NOR gates.
It is accordingly an object of the invention to provide a digital circuit having a filter unit for suppressing glitches which overcomes the above-mentioned disadvantages of the prior art devices of this general type, in which glitches in an input signal are suppressed without the signal propagation delays between the input signal and an output signal of the circuit being significantly increased as a result of this.
With the foregoing and other objects in view there is provided, in accordance with the invention, a digital circuit, including:
a signal input terminal;
at least two signal output terminals outputting final output signals;
switching elements each having a control input and each connected to one of the signal output terminals;
at least two logic circuit units for performing logic operations resulting in logic output signals, each of the logic circuit units having an input connected to the signal input terminal and an output connected to one of the signal output terminals via a respective one of the switching elements, a level change at the input of the logic circuit units results in a level change at the output of the logic circuit units; and
a filter unit having an input connected to the signal input terminal and an output connected to the control input of each of the switching elements, the filter unit suppressing glitches on a digital signal received at the input and outputs a filtered signal without the glitches at the output, the filtered signal being received by the control input of each of the switching elements for controlling operating states of the switching elements including a first operating state and a second operating state, in the first operating state of the switching elements the final output signals at the signal output terminals correspond to the logic output signals of the logic circuit units, in the second operating state of the switching elements the final output signals at the signal output terminals being independent of the logic output signals of the logic circuit units, the filter unit initially holding the switching elements in the second operating state prior to a level change of the digital signal at the signal input terminal and putting the switching elements into the first operating state in an event of the level change occurring after a time delay being longer than a signal propagation delay between the input and the output of one of the logic circuit units for which the signal propagation delay is greatest.
The digital circuit according to the invention has, between a signal input and at least two signal outputs, at least two logic circuit units whose outputs are connected to one of the the signal outputs of the digital circuit via a respective switching element. In this case, a level change of an output signal is established at the output of the logic circuit units in dependence on level changes of a signal at the input of the logic circuit unit. Furthermore, the digital circuit has a filter unit whose input is likewise connected to the signal input and whose output is connected to a control input of the switching elements, the filter unit suppressing glitches on a digital signal present at its input.
In the case of the invention, the input signal, which may be perturbed by glitches, at the signal input is fed unfiltered to the logic circuit units, which serve to carry out combinational logic functions (switching network), with the result that the output signal at the output of the logic circuit units is influenced by the glitches. In parallel with the logic circuit units, however, the input signal is also fed to the filter unit, which generates a filtered signal having fewer or, in the most favorable case, no glitches at all relative to the input signal. The filtered signal then serves for controlling the switching elements, which are expediently a logic gate, e.g. an AND or OR gate. The effect achieved by using the filtered signal to drive the switching elements is that those parts of the output signal of the logic circuit units which are influenced by the glitches in the input signal are not switched through to the signal outputs of the digital circuit.
The invention has the advantage that output signals which are free from glitches in the input signal at the signal input are obtained at the signal outputs of the digital circuit without the overall delay between these signals being significantly longer than the signal propagation delay through the logic circuit units. The digital circuit according to the invention is thus faster than the prior art circuits.
Other features which are considered as characteristic for the invention are set forth in the appended claims.
Although the invention is illustrated and described herein as embodied in a digital circuit having a filter unit for suppressing glitches, it is nevertheless not intended to be limited to the details shown, since various modifications and structural changes may be made therein without departing from the spirit of the invention and within the scope and range of equivalents of the claims.
The construction and method of operation of the invention, however, together with additional objects and advantages thereof will be best understood from the following description of specific embodiments when read in connection with the accompanying drawings.